1. Technical Field
Embodiments of the present disclosure relate to semiconductor devices and, more particularly, to semiconductor devices having bit line structures disposed in trenches, methods of fabricating the same, and packages, modules, and systems including the same.
2. Related Art
In general, semiconductor memory devices such as dynamic random access memory (DRAM) devices may include a plurality of cell transistors formed in and on active regions of a substrate. A first end (e.g., a source region) and a second end (e.g., a drain region) of each cell transistor may be connected to a storage node contact and a bit line contact, respectively. The storage node contacts may be electrically connected to cell capacitors, and the bit line contacts may be electrically connected to bit lines. As such, the cell transistors and the cell capacitors may act as memory cells of the semiconductor memory device. Recently, as semiconductor devices including memory devices become more highly integrated, critical dimensions (CDs) of lines constituting the cell transistors and the cell capacitors have been continuously reduced. Thus, the number of storage node contacts and bit line contacts integrated in a limited area has been increased.
As a result of the integration of semiconductor memory devices, a thickness of an interlayer insulation layer between the storage node contact and the bit line contact (or a bit line) may be reduced. Accordingly, the probability of an electrical short between a storage node contact and a bit line contact (or a bit line) adjacent to each other may increase, or a parasitic capacitance value between conductive lines may increase. Recently, various structures for improving electrical insulation characteristics between the storage node contact and the bit line contact (or the bit line) have been proposed. For example, a structure with a buried gate and a contact hole space is taught in US patent publication No. US 2012/0217576 A1. Further, a structure employing an air gap for preventing a parasitic capacitance value between the conductive lines from increasing is taught in US patent publication No. US 2012/0168899 A1.